Technical Leader

Company: Cisco Systems, Inc.
Location: San Jose
Posted on: November 19, 2024

Job Description:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.Your ImpactAs a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, power, and area specifications. This role involves coordinating cross-functional teams, guiding design methodologies, and addressing technical challenges throughout the development process to ensure successful tape-out and compliance with industry standards. Responsibilities include:

• Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results.
• Work with block and top-level implementation teams to understand physical aspects and feedback on necessary updates.
• Work closely with block and TOP level physical implementation, IP development teams and to resolve PV issues and address to proper owners.
• Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness.
• Support block and TOP implementation teams to solve local PV issues.Minimum Qualifications:
  • BS/MS in Electrical Engineering or Computer Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification
  • Experience with physical verification (DRC, LVS, ERC, ANT), debug, and solution.Preferred Qualifications:
    • Extensive experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support.
    • Experience on 5nm nodes and below.
    • Experience working with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams.
    • Experience working with Package and floorplan teams to define padring and bump-map design.
      #J-18808-Ljbffr

Keywords: Cisco Systems, Inc., Modesto , Technical Leader, IT / Software / Systems , San Jose, California